Accession Number:

ADA171742

Title:

Methodology Verification of Hierarchically Described VLSI Circuits,

Descriptive Note:

Corporate Author:

MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE

Personal Author(s):

• Bain, Isaac L.
• Glasser, Lance A.

Report Date:

1986-06-01

Pagination or Media Count:

18.0

Abstract:

The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circuit conformity to other kinds of rules. This is done at the transistor level, and most of the rules are user-selected. Two related issues are also discussed the description of digital MOS circuits using wiring operators and the formal description of methodologies by the designer. Author

Descriptors:

• *INTEGRATED SYSTEMS
• *COMPUTER AIDED DESIGN
• *INTEGRATED CIRCUITS
• *METAL OXIDE SEMICONDUCTORS
• COMPUTER PROGRAMS
• DIGITAL SYSTEMS
• GATES(CIRCUITS)
• TOPOLOGY
• CIRCUIT INTERCONNECTIONS
• AREA COVERAGE
• SYNTAX
• TRANSISTORS

Subject Categories:

• Electrical and Electronic Equipment
• Computer Programming and Software
• Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE