DID YOU KNOW? DTIC has over 3.5 million final reports on DoD funded research, development, test, and evaluation activities available to our registered users. Click HERE
to register or log in.
Methodology Verification of Hierarchically Described VLSI Circuits,
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
Pagination or Media Count:
The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circuit conformity to other kinds of rules. This is done at the transistor level, and most of the rules are user-selected. Two related issues are also discussed the description of digital MOS circuits using wiring operators and the formal description of methodologies by the designer. Author
APPROVED FOR PUBLIC RELEASE