DID YOU KNOW? DTIC has over 3.5 million final reports on DoD funded research, development, test, and evaluation activities available to our registered users. Click HERE
to register or log in.
A Parallel Processor for the Solution of Large, Sparse Symmetric Linear Systems.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH
Pagination or Media Count:
The need for rapid solution of large, sparse linear systems in certain applications is described. Conventional single processor computers are nearing fundamental speed limits, and will not be able to attain sufficient speeds. Parallel processing allows the application of a large number of processors to these problems, and thus has the potential to achieve faster operation. This dissertation describes a processor designed specifically for this type of problem. This system uses the technique of successive overrelaxation to obtain a solution to the linear system by iteration. The architecture features a separate processor for each variable in the linear system. The processors are arranged in a two dimensional grid, with connections to the four nearest neighbors. Each processor is partitioned into an Arithmetic Unit, which performs the actual computations, and a Communications Unit, to provide the necessary interchange of data between the processors. The design of the processor is described in detail. A detailed simulation is described which shows the performance and efficiency of the proposed system to be very high.
APPROVED FOR PUBLIC RELEASE