Delay Modeling of Bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) Circuits.
Final rept. Jan 85-Aug 86,
ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
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This report deals with the development of a delay-time model for timing simulation of large circuits consisting of Bipolar ECLEmitter-Coupled Logic and EFL Emitter-Follower-Logic networks. This model can provide adequate information on the performance of the circuits with a minimum expenditure of computation time. This goal is achieved by the use of proper circuit transient models on which analytical delay expressions can be derived with accurate results. The delay-model developed in this report is general enough to handle complex digital circuits with multiple inputs orand multiple levels. The important effects of input slew rate are also included in the model. Author
- Electrical and Electronic Equipment
- Computer Systems