A Design by Example: Regular Structure Generator.
MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
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This thesis investigates technical issues concerning the automated generation of highly regular VLSI circuit layouts e.g. RAMs, PLAs, systolic arrays that are crucial to the designability and realizability of large VLSI systems. The key is to determine the most profitable level of abstraction, which is accomplished by the introduction of true macro abstraction, interface inheritance, delayed binding, and the complete decoupling of procedural and graphical design information. These abstraction mechanisms are implemented in the Regular Structure Generator, an operational layout generator with significant advantages over first generation layout tools. Its advantages are demonstrated by a pipelined array multiplier layout example. A leaf cell compactor that can make the RSG technology transportable is also investigated. Author
- Electrical and Electronic Equipment
- Computer Hardware