Modified LDD Device Structures VLSI,
STANFORD UNIV CA INTEGRATED CIRCUITS LAB
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In LDD-like MOSFET structures previously studied, narrow, self- aligned n- regions are introduced between the channel and the n source-drain regions. In this paper, we describe a new n-MOS device structure which attempts to overcome some of the reliability problems of LDD devices. Instead of a pure n- region, we introduce a short-channel JFET under the sidewall oxide at the drain end in series with the intrinsic MOSFET. Both 2-D device simulations and experimental results are shown to demonstrate the operation of this device and its potential for VLSI applications.
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