Accession Number:

ADA169756

Title:

Totally Self-Checking Circuits and Testable CMOS Circuits.

Descriptive Note:

Technical rept.,

Corporate Author:

ILLINOIS UNIV AT URBANA COMPUTER SYSTEMS GROUP

Personal Author(s):

Report Date:

1986-06-01

Pagination or Media Count:

123.0

Abstract:

A Totally Self-Checking TSC circuit belongs to a class of circuits used for Concurrent Error Detection CED purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives and error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in nMOS. Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods which reduce the transistor count, delay, and the number of tests of TSC checkers are also given. Another problem in the area of TSC circuits concerns embedded checkers whose inputs are not directly controllable. If they do not get all the required codewords to test them they cannot be guaranteed to be TSC. A new encoding technique and a design procedure to solve this problem are presented. It has been shown previously that the two-pattern tests used to test CMOS circuits can be invalidated by timing skews. A necessary and sufficient condition is derived to find out whether or not an AND-OR or and OR-AND CMOS realization exists for a given function so that a valid test set can always be found, even in the presence of arbitrary timing skews. A new Hybrid CMOS realization is introduced to take care of the cases in which this is not possible. Keywords Encoding Fault models Self-checking circuits and Testability.

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE