Accession Number:

ADA169706

Title:

A Modified Lightly Doped Drain Structure for VLSI MOSFET's,

Descriptive Note:

Corporate Author:

STANFORD UNIV CA INTEGRATED CIRCUITS LAB

Personal Author(s):

Report Date:

1986-01-01

Pagination or Media Count:

48.0

Abstract:

A new n-MOS LDD-like device structure the J-MOS transistor is proposed. Its design, simulation and fabrication are studied in this paper. N-channel MOSFETs with L sub eff below 2 micrometers suffer from high field effects but their reliability is better than that of conventional MOSFETs only if the n- regions have a peak doping density above 1 x 10 to the 18th per cu. cm. To overcome this limitation and to allow constant voltage scaling for devices into the submicron regime, the J-MOS structure uses a series drain JFET to drop part of the supply voltage. Both 2-D device simulations and experimental results are presented to demonstrate the operation of this device and its potential for applications requiring reliable submicron device operation of this device and its potential for applications requiring reliable submicron device operation of this device and its potential for applications requiring reliable submicron device operation under maximum supply voltage. The major experimental findings are that the operation under maximum supply voltage. The major experimental findings are that the J-MOS structure can sustain 5V operation even for submicron effective channel lengths. As has been the case with all LDD-like structures, improved device reliability has been achieved at the expense of some performance. However, the advantages of keeping 5V operation in micron sized devices can outweigh this performance loss.

Subject Categories:

  • Electrical and Electronic Equipment
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE