Accession Number:

ADA167873

Title:

The RISC (Reduced Instruction Set Computer) Architecture and Computer Performance Evaluation.

Descriptive Note:

Master's thesis,

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

• Barros,Manuel F. P. de

Report Date:

1986-03-01

Pagination or Media Count:

97.0

Abstract:

A definition of Reduced Instruction Set Computers is developed. A computer performance model which allows the evaluation of architectural alternatives is presented. An example on the use of the model to compute the performance altenatives for a given application is presented to study the effect of the addition of an instruction to a processor instruction set. Keywords Theses Minicomputers. Author

Descriptors:

• *PERFORMANCE TESTS
• *COMPUTER ARCHITECTURE
• COMPUTERIZED SIMULATION
• COMPUTERS
• THESES
• PROCESSING EQUIPMENT
• REDUCTION
• INSTRUCTIONS
• MINICOMPUTERS

Subject Categories:

• Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE