Accession Number:

ADA167069

Title:

Hardware Implementation of a Concatenated Encoder/Decoder.

Descriptive Note:

Master's thesis,

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

Report Date:

1985-12-01

Pagination or Media Count:

49.0

Abstract:

This study describes the hardware implementation of a concatenated error correcting encoderdecoder. Individual burst and random error correcting coders were implemented using standard TTL integrated circuits and Z-80 microprocessors. The circuits handle input and output operations with a three line handshake. Thus, data transfer between circuits is asynchronous, and the coders may be concatenated in any order. Reed-Solomon, BCH, Golay, interleaving, and convolutional codes were considered. Of these codes, the BCH encoderdecoder, the Golay encoderdecoder, the interleaverdeinterleaver, and the convolutional encoder were all implemented in hardware. The Reed-Solomon encoderdecoder and the convolutional decoder will be implemented in a follow-on study in software. This study is the first part of a group of studies which will ultimately determine the actual error detection and correction performance of various concatenated coding schemes. Keywords Computer programs Assembly language. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE