The Simulation and Analysis of a RTL Model of the Motorola MC68000 Microprocessor with N.MPC. Volume 2. Appendices A-G.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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In a prior thesis project, a functional level model of portions of the Motorola MC68000 microprocessor was developed using signal analysis supported by limited technical data. Representative parts of the instruction set and exception processing structure were modeled with the Computer Design Language CDL. In this follow-on effort, those CDL models are transformed into equivalent models using ISP, an enhanced version of the Instruction Set Processor ISP hardware design language. This language transformation enabled the models to be simulated using N.mPc, a VAX 11780-hosted software package developed specifically to support the design of digital systems. To evaluate the correctness of the models, the simulation results are analyzed against signal data gathered with the aid of a logic analyzer during the actual operation of the MC68000 when processing the modeled instructions. The accuracy and completeness of the examined models suggests that this functional approach to microprocessor modeling is a valid one. Author
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