Modeling and Simulation of a Signal Processor Implementing the Winograd Fourier Transform.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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Continuing advances in the state of the art silicon fabriaction technology have allowed tremendous increases in the performance which may be achieved by a single integrated circuit. The natural counterpart of this increased functionality is, of course, increased design complexity. A growing problem is how to concisely and accurately communicate design information on VLSI and VHSIC class circuits. The VHSIC program office has sponsored the development of a hardware description language designed to address this problem. The VHSIC Hardware Description Language VHDL was applied to the problem of modeling a custom signal processor employing the Winograd Fourier Transform. A methodology was developed which decomposes the architecture into subcomponents, and then models the behavior and structure of the macrocells which comprise those subcomponents. Additionally, a custom simulator was developed to verify the timing, control, and hardware macrocells used in the implementation of the signal processor. The simulation modeled the circuit at the bit level and validated the architecture and expected numerical performance. Thesis
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