Content-Addressable Memory Manager: Design and Evaluation.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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This research covers basic issues in implementing a Content-Addressable Memory CAM for a microcomputer. The thesis compares the various types of CAM organizations and presents a set of standards to distinguish true CAM from CAM-like memory. Issues such as the meaning of content to the host computer are discussed. This discussion leads to the implementation issues of how the CAM should operate with the host computer. The two configurations addressed in detail a completely integrated approach and a peripheral approach. The thesis does not address the associative processor configurations found in PEPE, STARAN, or MPP. The case is presented that the peripheral device approach is the most practical approach. The peripheral device, CAM board, using the AFIT CAM IC chips, will be controlled from a dedicated device that is designed and evaluated in this thesis. The architecture and operation of the CAM IC chip controller CAM Manager is derived from the desire to have a general purpose device that will have a small instruction set. The instructions will allow for efficient operations on applications as diverse as LISP garbage collection, database searching, and array arithmetic. This thesis compares a conventional computer executing the test applications and the same computer using the CAM board. The test applications were a addition over all elements of an array, b LISP garbage collection, and c image recognition. The CAM board can enhance the performance of the host microcomputer. This initial implementation is not suited for large databases. This restriction was due to the size of the boards content-addressable memory 32K bits total.
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