Accession Number:

ADA163995

Title:

Design and Implementation of High Performance Content-Addressable Memories.

Descriptive Note:

Master's thesis,

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

Report Date:

1985-12-01

Pagination or Media Count:

106.0

Abstract:

The content-addressable memories CAMs have major applications in developing areas of artificial intelligence and image processing. This work involves researching, designing, and implementing a high performance, high density CAM. The design, fabrication, and test of this all-parallel AFIT CAM is discussed. The AFIT CAM stores 2K bits of information and fits in 64 pin dual-in-line package. It was fabricated using a 3 micron CMOS technology with 2-layer metals. The AFIT CAM supports four types of comparisons directly on the chip. These are equal, not-equal, greater-than-or-equal, and less-than. In addition, it has DUMP and Parallel Write operations to aid artificial intelligence and image processing applications. The AFIT CAM has a total of 78,000 devices and achieves a density of 1,073 devices per sq. mm. The memory access time for reading and writing are only 22 ns and 20 ns respectively. The CAM chip computes 800 million magnitude comparisons or 3.2 billion equality comparisons per second. The cif file has been resubmitted to the manufacturer for fabrication due to a short circuit which was caused by over bloated second metal lines. A second version of the AFIT CAM cell has been redesigned and nets a 25 reduction in size. Author

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE