An Analysis and Simulation of the CRAY X-MP Memory System.
MICHIGAN UNIV ANN ARBOR DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
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The CRAY X-MP 2- and 4-processor memory systems are analyzed and simulated using an instruction-level timing simulation of up to 16 processors. This study indicates a disturbing counter-intuitive trend to longer delays in vector accesses as both the number of processors and memory banks increase proportionately. This delay appears to be related to access start-up delays, which are determined for various memory organizations. Keywords include Supercomputers Simulation and Parallel processors.
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