A Parallel Stack Processor To Reduce Procedure-Call Overhead.
ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
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A processor organization is presented to reduce the large overhead of procedure calls in high-level languages. In the Parallel Stack Processor, processor registers are each at the top of a hardware stack of registers. Saving processor registers on procedure call takes place in one cycle by pushing all registers simultaneously. A detailed performance model, driven by dynamic high-level language statistics, is presented. Results from the model indicate the effect on performance of the parallel stack computer architecture when compared to a processor without parallel stacks. The processor architecture is specified in the report along with a discussion of implementation details for the VLSI single-chip processor. Keywords Parallel processors Stacking and Reduced Instruction Set Computer. Author
- Computer Programming and Software
- Computer Hardware