Accession Number:

ADA162494

Title:

A Parallel Stack Processor To Reduce Procedure-Call Overhead.

Descriptive Note:

Master's thesis,

Corporate Author:

ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB

Personal Author(s):

Report Date:

1985-11-01

Pagination or Media Count:

83.0

Abstract:

A processor organization is presented to reduce the large overhead of procedure calls in high-level languages. In the Parallel Stack Processor, processor registers are each at the top of a hardware stack of registers. Saving processor registers on procedure call takes place in one cycle by pushing all registers simultaneously. A detailed performance model, driven by dynamic high-level language statistics, is presented. Results from the model indicate the effect on performance of the parallel stack computer architecture when compared to a processor without parallel stacks. The processor architecture is specified in the report along with a discussion of implementation details for the VLSI single-chip processor. Keywords Parallel processors Stacking and Reduced Instruction Set Computer. Author

Subject Categories:

  • Computer Programming and Software
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE