Wafer-Scale Integration of Systolic Arrays,
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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VLSI technologists are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system or network of chips on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating wafer-scale systems around such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VSLI layout theory, graph theory, fault-tolerant systems and planar geometry. Keywords include Channel width Fault-tolerant systems Probabilistic analysis Spanning tree Systolic arrays Travelling salesman problem Tree of meshes VSLI Wafer-scale integration Wire length.
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