Accession Number:

ADA159824

Title:

A Systolic Array Implementation of a Reed-Solomon Encoder and Decoder.

Descriptive Note:

Master's thesis,

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1985-06-01

Pagination or Media Count:

93.0

Abstract:

A systolic array is a natural architecture for the implementation of a Reed-Solomon RS encoder and decoder. It possesses many of the properties desired for a special-purpose application simple and regular design, concurrency, modular expansibility, fast response time, cost-effectiveness, and high reliability. As a result, it is very will suited for the simple and regular design essential for VLSI implementation. This thesis takes a modular approach to the design of a systolic array based RS encoder and decoder. Initially, the concept of systolic arrays is discussed followed by an introduction to finite field theory and Reed-Solomon error correction codes. Then it is shown how RS codes can be encoded and decoded with primitive shift registers and implemented using a systolic architecture. In this way, the reader can gain valuable insight and comprehension into how these entities are coalesced together to produced the overall implementation. Additional keywords Systolic multipliers. Author

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE