Accession Number:

ADA159433

Title:

VLSI (Very Large Scale Integrated) Design of a Sixteen Bit Pipelined Multiplier Using three Micron NMOS Technology.

Descriptive Note:

Master's thesis,

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1985-06-01

Pagination or Media Count:

95.0

Abstract:

The application of computer-aided design CAD tools in the full custom design and testing of a 16-bit pipelined twos complement multiplier in three micron NMOS is described. A comparison between the full custom carry-save addition CSA multiplier designed using CAD tools and a multiplier generated by the MacPitts silicon compiler is presented. Additional background material is also presented on the CSA multiplication algorithm used. Keywords NMOS VLSI design Pipelined multiplier Twos complement multiplier CAD tools MacPitts silicon compiler VLSIVery Large Scale Integration Integrated CircuitsTheses.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE