Bulk CMOS VLSI Technology Studies. Part 4. Design of a CMOS Microsequencer.
Final rept. Aug 82-Feb 85,
MISSISSIPPI STATE UNIV MISSISSIPPI STATE DEPT OF ELECTRICAL ENGINEERING
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This thesis discusses the design of a CMOS microsequencer used in a microprogrammed control organization. A preconceived data path performs most of the data manipulation functions for an LSI computer system. The operations are performed as directed by sequences of control microinstructions, which are fetched from a microcode memory using addresses generated by the microsequencer chip. A Programmable Logic Array PLA is selected in lieu of random logic to control the circuits within the microsequencer. Extensive use has been made of clocked CMOS over classic CMOS to achieve higher layout density and better performance. The chip has been designed using scalable design rules which means it can be fabricated in 1.2 micron or 3 microm technology. The design used double-layer metal, eliminating the need for extensive poly-interconnect lines. Author
- Electrical and Electronic Equipment
- Computer Programming and Software