Bulk CMOS VLSI Technology Studies. Part 3. A 1.2 Micron CMOS Data Path Chip.
Final rept. Aug 82-Feb 85,
MISSISSIPPI STATE UNIV MISSISSIPPI STATE DEPT OF ELECTRICAL ENGINEERING
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A 16-bit, 1.2 micron CMOS data path chip is presented. The chip consists of two IO ports, a 22 register scratch pad memory, a general purpose ALU, and a barrel shifter. The chip is designed to operate with a two-phase clock and is microcode controlled by a 22-bit phase 1 microword and a 13-bit phase 2 microword. The chip has a 64-pad frame with 3 pads not connected. The circuitry and layouts for this data path chip are presented. How the chip can be functionally tested is included, and enhancements for a second generation chip are discussed.
- Electrical and Electronic Equipment