Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design.
Final rept. Aug 82-Feb 85,
MISSISSIPPI STATE UNIV MISSISSIPPI STATE DEPT OF ELECTRICAL ENGINEERING
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Part 1 Scalable CMOS design rules are developed for the MOSIS community to facilitate fabrication from a single design at 3 microns and 1.3 microns VHSIC dimensions. Part 2 Various Programmable Logic Array PLA implementations with clocked CMOS technology are explored in this project. Three different CMOS PLA circuit styles are described the large PLA uses a gated OR plane and is useful for a system with large number of inputs the moderate PLA and the small PLA are ripple varieties with the former having the capability of handling a larger number of inputs than the latter. Path Programmable Logic PPL, which is a folded form of a PLA, is also studied. A symbolic form of representation is developed and future PPL development activities are discussed. The PPL approach has a size and flexibility advantage over the other PLA approaches - except in applications requiring large PLAs.
- Electrical and Electronic Equipment
- Computer Programming and Software