Design of a Sixteen Bit Pipelined Adder Using CMOS Bulk P-Well Technology.
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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The design of a sixteen-bit pipelined adder complementary metal oxide semiconductor circuit is presented. The adder is designed to maximize throughput and to provide for testability. Tutorial material on CMOS design is also presented. Additional keywords theses VLSIvery large scale integration computer aided design NMOSnegatively doped metal oxide semiconductors logic circuits. Author.
- Electrical and Electronic Equipment