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Accession Number:
ADA151834
Title:
Designing VLSI (Very Large Scale Integrated) Circuits for Testability.
Descriptive Note:
Master's thesis,
Corporate Author:
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
Report Date:
1984-12-01
Pagination or Media Count:
137.0
Abstract:
Very large scale integrated circuits are difficult to test once fabricated. This is due to the large number of internal circuit nodes that are not accessible as probe points, and the small number of primary inputs and outputs available to exercise and observe these internal nodes. Methods to develop test vectors for such circuits e.g. d-Algorithm are both difficult and time consuming. For this reason a method is needed to design circuits which are highly testable or self-testing. Using computer aided design tools, a circuit is designed which exhibits a self-test scheme. The design concepts used include a level-sensitive scan design and signature analysis. When completed the circuit is evaluated from the standpoint of how much design effort, circuit area used, and test effort compares with the same parameters for a circuit without testability characteristics included. Environmental dependency the conditions of circuit operation is an important consideration when determining if self-test capability is warranted. When the circuit is one which is inaccessible after deployment or needed without much testing time available, self-test capability is worthwhile. This is a very necessary capability for satellite systems or systems which must be replaced without delay e.g. component of F-16 fire control system. Originator supplied keywords include Integrated circuits VLSI testing Self-testing Test methods and Testability.
Distribution Statement:
APPROVED FOR PUBLIC RELEASE
