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A New Microelectronic Workstation for VLSI (Very-Large-Scale-Integrated) Layout Design.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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Recent advances in microelectronic technology have allowed for the integration of complex very-large-scale-integrated VLSI circuits on a single chip. In this regard, metal-oxide-semiconductor MOS technology has been the only means by which this single-chip integration has been possible for both analog and digital circuits. Although there are several steps involved in the overall VLSI design process, this thesis will focus on the layout design. VLSI layout design is a very time consuming process and, therefore, makes extensive use of both hardware and software computer aids. This thesis deals with the development and testing of a new microelectric workstation which will be used specifically for VLSI layout design. The operation and design methodologies of MOS VLSI circuits, with emphasis on the layout, are examined.
APPROVED FOR PUBLIC RELEASE