Accession Number:

ADA151718

Title:

Automatic VLSI (Very Large Scale Integration) Routing Using 2-Layer Metal.

Descriptive Note:

Master's thesis,

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

• Hewitt,T. G.

Report Date:

1983-12-01

Pagination or Media Count:

140.0

Abstract:

The program minimizes the channel height of a channel. The channels must be rectangular. Also, each horizontal channel must intersect every vertical channel and vice versa. Alternate paths can be found for nets in horizontal channels when channel capacity is exceeded. Constraint loops are removed by ordering the way nets are routed or by introducing a dogleg. The program produces output that is compatible with CLL Chip Layout Language. The output from the program can be merged with CLL statements that place cells from a library on a grid to form plots or to create CIF Caltech Intermediate Form data to be used in making VLSI chips. Author

Descriptors:

• *INTEGRATION
• CAPACITY(QUANTITY)
• GRIDS
• PATHS
• VERTICAL ORIENTATION
• HORIZONTAL ORIENTATION
• HEIGHT
• CHANNELS

Subject Categories:

• Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE