Design of a Bit-Sliced Processor Array with Built-In-Self-Test.
ILLINOIS UNIV AT URBANA COMPUTER SYSTEMS GROUP
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The overall objective of this report is to present an integrated approach to the design of bit-sliced processor arrays with built-in self-test. The conventional approach of making each bit-sliced processor chip self-testing is not used. Rather, a new approach of using an extra chip to test a processor array fo any size and itself is used. The classical stuck-at fault model is not suitable for VLSI circuits. Rather, a functional level fault model is used. Ech module of the processor array is tested exhaustively. The test responses of a fault-free processor array are made identical so that they can be easily monitored with no loss in fault coverage. The tester chip tests itself while it is testing the processor array. The fault coverages for both the tester chip and the processor array are high the performance degradation is minimal the area overhead is low, especially for large processor arrays and the test length is short so tests can be performed more frequently. A VLSI design of the tester chip has been done with a 2-microns NMOS process. Author
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