Built-In Tests for VLSI (Very Large Scale Integration) Finite-State Machines.
ILLINOIS UNIV AT URBANA COMPUTER SYSTEMS GROUP
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The introduction of LSIVLSI technology has increased the difficulty of both designing and testing the complex systems which can be implemented to a chip. The testing problem, especially, is felt to be the primary bottleneck to the widespread use of the next generation of VLSI chips. Design for testability has been proposed as a solution to this problem. We have developed a built-in test scheme for VLSI finite-state machines using PLAs. Unlike other built-in test schemes for PLA. The difficulty in interconnecting the test logic and the naked PLA is considered. The layout has been done for the test logic cells and example PLA in nMOS technology to demonstrate that all the test logic cells line up perfectly with the PLA cells. This eliminates the interconnection problems. This scheme, using a universal test set, allows a finite-state machine implemented with a PLA to be tested with in a number of cycles that is proportional to the number of inputs and product terms. By modifying the single-bit decoders, a test pattern generator is available for testing of the AND-plane at a low cost. The use of the feedback NOR gates of the Augmented Decoder to detect stuck-at faults and short faults of the columns in the AND-plane saves a lot of hardware since another parity checker would otherwise have to be used. By using the multiplexing scheme, the sizes of the shift registers are also cut down in half compared with other PLA testing schemes.
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