Research into Self-Timed VLSI Circuits.
PRINCETON UNIV NJ DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
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ALLENDE is a simple and powerful layout language, associated with a structured design methodology for VLSI. It has a combination of features that set it apart from the existing VLSI layout tools. These features include the procedural language approach, the structured specification of the layout, the use of constraints to represent the layout, and the use of an intermediate form in the implementation of the system. In ALLENDE the layout is described hierarchically as a composition of cells absolute sizes or positions are never specified. The layout description is translated into linear constraints, which express design rules and relative position of the layout elements. By solving these constraints we obtain the absolute layout, which is guaranteed to be free of design rule violations. Errors in the layout description are immediately detected and easily located. ALLENDE consists of five procedures to be called from a Pascal or C program, allowing the user to describe a VLSI layout. A lot of parameterization is possible when specifying layout elements, besides the ability to make use of the full power of Pascal or C. The ALLENDE layout system has been implemented for the nMos technology. In this system we can also use cells generated by other layout tools. Our layout language can also be a target for a silicon compiler.
- Electrical and Electronic Equipment