Accession Number:

ADA142377

Title:

A Simulation Program with Latency Exploitation for the Transient Analysis of Digital Circuits.

Descriptive Note:

Master's thesis,

Corporate Author:

ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB

Personal Author(s):

• Sohail,S. A.

Report Date:

1983-08-01

Pagination or Media Count:

85.0

Abstract:

This report examines the efficiency that can be obtained in the simulation of large digital integrated circuits with the implementation of latency, that is, inactive gates in a given time interval are bypassed in the simulation. In particular the latency criterion in the program SLATE is studied, and a users guide to SLATE is included. Author

Descriptors:

• *DIGITAL SYSTEMS
• *INTEGRATED CIRCUITS
• *CIRCUIT TESTERS
• USER MANUALS
• SIMULATION
• TRANSIENTS
• TIME INTERVALS
• GATES(CIRCUITS)
• CIRCUITS
• INACTIVATION

Subject Categories:

• Electrical and Electronic Equipment
• Test Facilities, Equipment and Methods

Distribution Statement:

APPROVED FOR PUBLIC RELEASE