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A Simulation Program with Latency Exploitation for the Transient Analysis of Digital Circuits.
ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
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This report examines the efficiency that can be obtained in the simulation of large digital integrated circuits with the implementation of latency, that is, inactive gates in a given time interval are bypassed in the simulation. In particular the latency criterion in the program SLATE is studied, and a users guide to SLATE is included. Author
APPROVED FOR PUBLIC RELEASE