Accession Number:

ADA142142

Title:

VLSI Research

Descriptive Note:

Semi-annual technical research and development status rept. Oct 1983-Apr 1984

Corporate Author:

CALIFORNIA UNIV BERKELEY

Personal Author(s):

Report Date:

1984-04-01

Pagination or Media Count:

1543.0

Abstract:

A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR Smalltalk On a RISC, should run program s4-15 times faster than the Xerox 1100 Dolphin, a TTL minicomputer, and about as fast as the Xerox 1132 Dorado, a 100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release 4.2. The Magic formerly called Caddy layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystals estimates were within 5-10 of SPICEs estimates, while being a factor of 10,000 times faster.

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE