Design Study of Floating Point Systolic VLSI Chip.
HUGHES RESEARCH LABS MALIBU CA
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The objective of this program was to investigate the feasibility of building a floating point processor 24-bit mantissa and 8-bit exponent on a single ship based on the Hughes Research Laboratories HRL present 28-bit fixed point chip Multiplication Oriented Processor or MOP chip. The plan was to generate any necessary cell logic, layout, or simulations in order to estimate the size of the chip and predict its performance. Since division and square root were not included in the HRL MOP chip, arithmetic algorithms for performing these operations were to be studied. Author
- Electrical and Electronic Equipment
- Theoretical Mathematics