A CRAY-Class Multiprocessor Simulator.
MICHIGAN UNIV ANN ARBOR SUPERCOMPUTER ALGORITHM RESEARCH LAB
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A logical-timing instruction-level simulator is described for a hypothetical multiprocessor consisting of CRAY-1s connected to a common memory. It is useful for gaining insight into the design of multiprocessor algorithms and for developing high performance algorithms for CRAY processors with instruction sets similar to the CRAY-1. Author
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