A Framework for Solving VLSI (Very Large Scale Integration) Graph Layout Problems.
Interim research rept.,
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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This paper introduces a new divide- and conquer framework for VLSI graph layout. Universally close upper and lower bounds are obtained for important cost functions such as layout area and propagation delay. The framework is also effectively used to design regular and configurable layouts, to assemble large networks of processors using restructurable chips, and to configure networks around faulty processors. It is also shown how good graph partitioning heuristics may be used to develop a probably good layout strategy. Author
- Electrical and Electronic Equipment
- Numerical Mathematics