LSI (Large Scale Integrated) Design for Testability. Final Report of Design, Demonstration, and Testability Analysis.
Rept. for 5 Jul 79-15 Dec 80,
IBM FEDERAL SYSTEMS DIV MANASSAS VA
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The objective of this effort was to demonstrate IBM Level Sensitive Scan Design methodology as an approach for improving the testability of military LSIVLSI circuits. LSSD was demonstrated in an LSI component AP101C test bed to be a viable and attractive design approach for military LSIVLSI components. Author
- Administration and Management
- Electrical and Electronic Equipment
- Test Facilities, Equipment and Methods