The Extension and Application of Global Compaction Techniques for Horizontal Scientific Code.
Final 1 Sep 81-31 Aug 83,
YALE UNIV NEW HAVEN CT DEPT OF COMPUTER SCIENCE
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This report summarizes the work completed in applying trace scheduling to the Floating Point Systems AP164 array processor. This ongoing project focuses upon trace scheduling. The two main aspects of the proejct are the development of a trace scheduling compiler and to design a single instruction multiple data SIMD floating point machine that is optimized for trace scheduling. The aspect of this project which has been done under this ARO grant was the development of a trace scheduler for the AP164 attached processor. This architecture is the most common example of a SIMD machine for which the user writes code. The AP164 offers limited parallelism in that it has three alus and a limited cross-bar.
- Numerical Mathematics
- Computer Programming and Software
- Computer Hardware