A Structured Design Methodology for VLSI Systems.
Final rept. Aug 80-31 Jul 83,
STANFORD UNIV CA STANFORD ELECTRONICS LABS
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New algorithms and tools for hierarchical design and verification of IC chips have been developed. The multi-level simulation capabilities of SABLE have been extended using the ADA language. Automatic synthesis of stick diagrams from net lists and subsequent pitch-constrained compaction of layout provide new capabilities for cell generation. New parallel algorithms for routing and design rule checking have been developed which are orders-of-magnitude faster than conventional approaches. Analytic models to accurately estimate and bound waveforms in MOS circuits have been developed and provide new insight for performance enhancement. Author
- Electrical and Electronic Equipment
- Solid State Physics