Advanced On-Board Signal Procesor GaAs Memory.
Final technical rept. 21 Jan 1981-21 Oct 1982
ROCKWELL INTERNATIONAL THOUSAND OAKS CA MICROELECTRONICS RESEARCH AND DEVELOPMENT CENTER
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This report covers the first twenty-one months of the AOSPAdvanced On-Board Signal Processor GaAsGallium Arsenide Memory Program. The objective of this program is to utilize the performance advantages offered by GaAs integrated circuits in the areas of radiation hardness, low power dissipation and high speed for the development of a 4K bit RAM. The DARPA process development program has complemented and provided a sound basis for the initial progress made in this RAM program. Using the existing GaAs technology as a base, the authors have initially focused their efforts on process areas unique to RAMS, on evaluation of the power concentration RAM Random Access Memory cell and on the design and fabrication of a 256 bit static memory chip. The development of operational 256 bit memory arrays has been used on three mask sets namely AP1, RM2, and RM3. Mask set AP1 contained preliminary RAM cell designs for verification of design concepts and layout rules while RM2, using data obtained from AP1, focused on the design, fabrication and evaluation of 256 bit RAMs. The RM3 mask set was used to initiate the processing of 3 in. GaAs wafers, and at the same time to fabricate a fully functional 256 bit static RAM.
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