Automated Synthesis of Digital Hardware Modules: Simulation and Verification of Interconnections.
Final rept. Sep 80-Aug 83,
UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES DEPT OF ELECTRICAL ENGINEERING
Pagination or Media Count:
The final report describes research in hardware synthesis, layout, compaction and area estimation. The most important results involve the wireability analysis for gate arrays, the derivation of Rents rule, extensions of Hafers register-transfer synthesis model, and the specification of a data structure to represent hardware design data for use in an expert system. Author
- Computer Programming and Software
- Computer Hardware