Upset Response Testing Of MSI Integrated Circuits.
Final rept. 1 Jun 80-15 Jan 82,
BOEING AEROSPACE CO SEATTLE WA
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This study developed a standard test method for determining the upset response threshold of MSI integrated circuits. Differences in the upset response of internal logic cells were found that were caused by geometrical differences in the design and layout of internal transistors. An analysis method was developed and incorporated into the test standard which can identify these sensitive locations, providing a basis for selecting operating conditions for upset response testing.
- Electrical and Electronic Equipment
- Nuclear Radiation Shielding, Protection and Safety