Accession Number:

ADA126363

Title:

RAPIDbus Architecture and Realization.

Descriptive Note:

Interim rept.,

Corporate Author:

CARNEGIE-MELLON UNIV PITTSBURGH PA ROBOTICS INST

Personal Author(s):

Report Date:

1982-11-01

Pagination or Media Count:

90.0

Abstract:

RAPIDbus Architecture and Realization describes a synchronous multiprocessor designed to support sensory processing, image understanding, and control applications. Up to eight board level masters interact with up to eight slaves along a time-multiplexed implementation of a crossbar switch. Two implementations are considered, one based on an Advanced Shottky logic with a bus bandwidth of 16 Mhz and a Versabus host interface. The second implementation, based on an ECLTTL gate array, permits an estimated 64 Mhz of bus bandwidth and a VersusMultibus host interface. Segmented memory management a multicast capability between one master and multiple destinations, and a standardized host interface aid in making RAPIDbus an appropriate architecture for robotic applications. Author

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE