Accession Number:

ADA126156

Title:

Leadless Chip Carrier Packaging and CAD/CAM (Computer-Aided Design/Computer-Aided Manufacturing) Supported Wire Wrap Interconnect Technology for Subnanosecond ECL (Emitter Coupled Logic).

Descriptive Note:

Interim technical rept. 1 Jul 81-30 Jun 82,

Corporate Author:

MAYO CLINIC ROCHESTER MN SPECIAL PURPOSE PROCESSOR DEVELOPMENT GROUP

Personal Author(s):

Report Date:

1982-12-01

Pagination or Media Count:

236.0

Abstract:

This document is the third year interim report for a four-year program to refine and develop Computer-Aided Design protocols for implementation of subnanosceond Emitter Coupled Logic in High-Speed Computer Modules using a wire wrap interconnection medium. The software and user manual for implementation guides are not part of the actual report. This report describes the results of work conducted in the third year of a four year program to develop rapid methods for designing and prototyping high-speed digital processor systems using subnanosecond emitter coupled logic ECL. The third year effort was divided into two separate sets of tasks. In Task 1, described in Sections III-VII of this report, we have nearly completed development of new sets of design rules, interconnection protocols, special components, and logic panels, for a technology based upon specially designed leadless ceramic chip carriers developed at Mayo Foundation. Task 2, described in Sections VIII and IX of this report, continued the development of a comprehensive computer-aided designcomputer-aided manufacturing CADCAM software package which is specifically tailored to support the peculiar design requirements of processors operating in a high clock rate, transmission line environment, either with subnanosecond ECL components or with any other families of subnanosecond devices.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Computer Hardware
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE