Accession Number:

ADA123328

Title:

Design and Implementation of a Single-Chip 1-D Median Filter.

Descriptive Note:

Interim rept.,

Corporate Author:

CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE

Personal Author(s):

Report Date:

1982-04-01

Pagination or Media Count:

28.0

Abstract:

The design and implementation of a 1-Dimensional median filter in VLSI is presented. The device is designed to operate an 8-bit sample sequences with a window size of 5 samples. Extensive pipelining and employment of systolic concepts at the bit level enable the chip to filter at rates up to 10 Mega-samples per second. The chip is designed to be implemented with a lambda 2.5 micro NMOS technology and is 6.2 mm by 5.0 mm in size. A circuit configuration for using the chip in approximate 2-D median filtering is also presented.

Subject Categories:

  • Electrical and Electronic Equipment
  • Theoretical Mathematics
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE