Processor Displacement: An Area-Time Trade-off Method for VLSI Design.
Interim technical rept.,
PURDUE UNIV LAFAYETTE IN DEPT OF COMPUTER SCIENCES
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Direct VLSI implementation of pipelined systolic processor arrays can lead to an over parallelized design causing the chip to have unused or underutilized area. Processor displacement design is a methodology that provides a spectrum of designs with differing time-area trade offs. The methodology is motivated, presented in detail, and illustrated by several examples. Direct experience for the Transitive Closure and Dynamic Programming systolic arrays is presented. Author
- Electrical and Electronic Equipment
- Computer Hardware