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An Implementation of MIL-STD-1750 Airborne Computer Instruction Set Architecture.
ROYAL AIRCRAFT ESTABLISHMENT FARNBOROUGH (ENGLAND)
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This Memorandum describes the design of a processor implementing the Mil-Std-1750 Airborne Computer Instruction Set Architecture, using Advanced Micro Devices 2901 bit-slice microprocessor devices. The aspects of the hardware design and microcode specific to Mil-Std-1750 are discussed and reviewed in the light of the experience gained. A full listing of the AMD AMDASM micro assembler definition file and microcode source text is included, together with a full hardware documentation. Author
APPROVED FOR PUBLIC RELEASE