Introduction to the Configurable Highly Parallel Computer. Revision.
Interim technical rept.,
PURDUE UNIV LAFAYETTE IN DEPT OF COMPUTER SCIENCES
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The Configurable, Highly Parallel CHiP Computer family is introduced. These architectures are built around a lattice of programmable switches and data paths that permit processing elements to be connected in arbitrary patterns. The approach preserves locality. The parameters that determine various family members are discussed including switch configuration storage capacity, switch and processor element degrees and corridor width. An efficient embedding of a complete binary tree is presented to illustrate interconnection pattern programming. An algorithm for solving a system of linear equations is given to illustrate the versatility of configurability. Author
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