Accession Number:

ADA099776

Title:

Introduction to the Configurable Highly Parallel Computer. Revision.

Descriptive Note:

Interim technical rept.,

Corporate Author:

PURDUE UNIV LAFAYETTE IN DEPT OF COMPUTER SCIENCES

Personal Author(s):

Report Date:

1981-05-18

Pagination or Media Count:

35.0

Abstract:

The Configurable, Highly Parallel CHiP Computer family is introduced. These architectures are built around a lattice of programmable switches and data paths that permit processing elements to be connected in arbitrary patterns. The approach preserves locality. The parameters that determine various family members are discussed including switch configuration storage capacity, switch and processor element degrees and corridor width. An efficient embedding of a complete binary tree is presented to illustrate interconnection pattern programming. An algorithm for solving a system of linear equations is given to illustrate the versatility of configurability. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE