Accession Number:

ADA091952

Title:

Feasibility Study of the Combination of MNOS Elements and Bipolar TTL Peripherals on an LSI Circuit Chip.

Descriptive Note:

Final technical rept. 29 Sep 78-29 Jun 79 on Phase 1,

Corporate Author:

RCA SOLID STATE DIV SOMERVILLE NJ

Personal Author(s):

Report Date:

1980-08-01

Pagination or Media Count:

209.0

Abstract:

The objective of this research was to obtain radiation, reliability, and performance data on monolithic test structures containing MNOS memory transistors and n-p-n bipolar transistors. The data indicates that the devices performed acceptably at 100,000 rads Si. Thin-oxide structures performed satisfactorily after exposure to 500,000 radsSi. Thus, if these devices were combined into an EAROM memory circuit, a hardness level above 100,000 rads should result. Performance, reliability, and breakdown characteristics were measured and are consistent with parameter values that would be useful for an EAROM.

Subject Categories:

  • Electrical and Electronic Equipment
  • Nuclear Radiation Shielding, Protection and Safety

Distribution Statement:

APPROVED FOR PUBLIC RELEASE