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Dynamic Properties of Electronic Trapping Centers at the Si-SiO2 Interface.
Final rept. 29 Jun 79-30 Jun 80,
XEROX PALO ALTO RESEARCH CENTER CA
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The Si-SiO2 interface possesses defects which may be considered characteristic of the thermal oxidation process. Electronic defects introduce a broad peak in the interface-state distribution which is centered approximately 0.3eV above the silicon valence-band maximum. Furnace anneals remove these levels yielding the generally observed U-shaped distribution. The ESR interface defect was evaluated over a range of annealing temperatures less than or equal to 600 C. The spin signal rapidly decays in MOS structures annealed above 250 C. An anneal in atomic deuterium at 230 C completely annihilated the spin center, which could not be recovered with vacuum anneals up to 600 degrees C. The surface-potential dependence of the interface spin center was investigated in order to further establish the correlation between the paramagnetic defect and interface states. It was found that the ESR amplitude changes reversibly by approximately 25 as the surface potential is adjusted between inversion and accumulation conditions. Author
APPROVED FOR PUBLIC RELEASE