Noncoplanar High Power FET.
Final rept. Dec 74-Nov 78,
VARIAN ASSOCIATES INC PALO ALTO CA SOLID STATE LAB
Pagination or Media Count:
Using a p substrate as the gate and employing low-doped V-grooves under the source and drain to reduce parasitic capacitances, a noncoplanar power FET was designed and fabricated which achieved submicron gate lengths with photolithography masks employing a resolution limit of several microns. Device performance was limited by low values of pinch-off voltage and gate breakdown voltage. Ion imlantation or diffusion should enable the breakdown voltage to be raised by virtue of separating the p-n junction from the growth interface.
- Electrical and Electronic Equipment
- Solid State Physics