The Use of Al(x)Ga(1-x)As Buffer Layers to Reduce Parasitic Space Charge Limited Current Flow through the Substrate in FET Structures,
CORNELL UNIV ITHACA N Y SCHOOL OF ELECTRICAL ENGINEERING
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A simple analysis has been made of the parasitic space charge limited current flow in a GaAs substrate or buffer. The computed output conductance is in agreement with experimental values of 600 to 1000 ohms obtained on low noise FETs with 300 micron gate width fabricated on GaAs buffer layers with low trap density. The parasitic current flows in the semi-insulating substrate or buffer layer, around the thin high field Gunn domain that is present in the active layer of the FET. Including the effects of changing domain length with drain bias, the parasitic current is found to rise as the square root of the drain voltage and as the 4th root of the active channel doping.
- Solid State Physics