Multimode CPU Design Study.
Final rept. May 77-May 78,
LITTON SYSTEMS INC VAN NUYS CALIF DATA SYSTEMS DIV
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A study was conducted to define a Multimode CPU architecture in which the CPU could handle instruction addressing, data addressing, and data processing. A problem set of signal processing tasks was defined from which the architectural design evolved. The multiplierFFT interaction was identified as a major architectural constraint. A RALU structure was defined to perform the data addressing and data processing. A microsequence structure was designed to perform the instruction addressing. Two complex-data signal processors were defined and designed at the register level. These processors, along with the Raytheon Micro Signal Processor and the TracorRCA General Processing Unit were addressed on their ability to perform benchmarks from the initial problem set. Author
- Computer Hardware